1. Field of the Invention
The invention relates to high performance wireless transceiver circuits, and more particularly to an on-chip bandstop and bandpass CMOS filter fully integrated into one unit where all inductors are integrated on the chip.
2. Description of the Related Art
With the growing market in wireless communications, high performance wireless transceiver chips are required to meet the demand of high data rate and wide-band services. This development has driven the wireless industry to develop new design techniques for the transceiver. Architectures such as low intermediate frequency (IF) receivers and zero-IF (direct conversion) receivers have been proposed to overcome problems in classical superheterodyne receivers. Refer to                J. Crols and M. Steyaert, CMOS Wireless Transceiver Design, Kluwer Academic Publishers, 1997, pp. 13–19, and pp. 63–66;        T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, U.K.: Cambridge Univ. Press, 1998, pp. 550–559;        B. Razavi, RF Microelectronics, NJ: Prentice Hall, 1998, pp. 122–129, 138–143;        J. Crols and M. Steyaert, “A Single-Chip 900 MHz CMOS Receiver Front-End with a High Performance Low-IF Topology,” IEEE Journal of Solid State Circuits, vol. 30, no. 12, pp. 1483–1492, December 1995.        
The low IF architecture in J. Crols and M. Steyaert, CMOS Wireless Transceiver Design, and “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology” as referenced above, combines the advantages of both the superheterodyne and the zero-IF receiver. It can achieve good performance as well as high degree of integration. The main problem of the low IF receiver is the difficulty to attain high image rejection. Although complex filters and/or polyphase filters have been invented to reject the image signal in low IF receivers, the image rejection ratio (IRR) provided by these methods is very sensitive to I/Q amplitude imbalance and phase mismatch of the receiver path. As a result, the current low IF receivers only can attain about 30–40 dB image rejection.
The direct conversion architecture in T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, and B. Razavi, RF Microelectronics, as referenced above, alleviates the problem of image rejection and has good performance with a small noise figure, high linearity and low complexity. However, it possesses some other serious problems such as DC offset, flicker noise, IP2 nonlinear distortion, and so on.
The superheterodyne receiver perhaps is the most commonly used transceiver architecture in wireless industry. As illustrated in FIG. 1a (prior art), it normally includes a bandpass filter (BPF) 11, a low noise amplifier (LNA) 12, an image rejection filter (IMR-F) 13, also called a notch filter, and a downconversion mixer 14 in the RF band. In most RF applications the image signal can be over 60 dB higher than the desired RF signal, so the overall image rejection ratio (IRR) must be 60 to 70 dB as per B. Razavi, RF Microelectronics, above, to make the receiver function properly. Due to unavoidable process and temperature variations, the current integrated image rejection mixer only can attain about 30 dB of image rejection. The other 30–40 dB of image rejection has to be done by employing an RF image rejection filter between the LNA and mixer. The current RF filters used for band selection and image rejection are mainly off-chip filters like ceramic and SAW filters, these types of filters are usually bulky and very costly, furthermore, they are not integratable and consume more power. Moreover, they need impedance matching both at the input and output to work well. These extra constraints have to be imposed on the preceding LNA design and the following mixer design.
To solve these problems, and to achieve a fully integrated, low cost, low power and single chip radio-frequency integrated circuit (RFIC) solution, the present invention proposes an on-chip bandstop filter (for image rejection) and bandpass filter (for band selection) integrated into one unit 15, as illustrated in FIG. 1b. By adding an LC tank into the output matching network of an LNA, an on-chip bandpass filter can be realized. To further improve the filter performance a Q-enhancement circuit can be used for Q-tuning of the bandpass filter. In the following recent articles, on-chip notch filters have been proposed to reject the image signal, which can provide good noise and linearity performance:                Chunbing Guo, A. N. L. Chan, and H. C. Luong, “A Monolithic 2-V 950-MHz Bandpass Amplifier with A Notch Filter for Wireless Receivers,” IEEE Radio Frequency Integrated Circuits Symposium, 2001, pp. 79–82.        Yuyu Chang, J. Choma, Jr. and J. Wills, “An Inductorless Active Notch Filter for RF Image Rejection,” Proc. IEEE Int. Symp. on Circuits and Systems, 1999, pp. 166–169.        H. Samavati, H. R Rategh, and T. H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End,” IEEE Journal of Solid State Circuits, vol. 35, no. 5, May 2000, pp. 765–772.        M. H. Koroglu and P. E. Allen, “LC notch filter for image-reject applications using on-chip inductors,” Electronics Letters, Mar. 1, 2001, vol. 37, No. 5, pp. 267–268.        J. Macedo, M. Copeland, and P. Schvan, “A 2.5 GHz monolithic silicon reject filter,” IEEE 1996 Custom Integrated Circuits Conference, pp. 193–196.        J. W. M. Rogers and C. Plett, “A Completely Integrated 1.8 Volt 5 GHz Tunable Image Reject Notch Filter,” IEEE Radio Frequency Integrated Circuits Symposium, 2001, pp. 75–78.        
Since usually low Q inductors are used in the design of LC notch filters the adding of a Q-enhancement circuit is necessary because it would improve the equivalent Q value of the filter and achieve a deeper notch response. Although a simple Q-enhancement circuit is cheap to implement, it needs a large DC bias current to achieve a good notch filter response. For this reason, a development of a notch filter with a low complexity Q-enhancement circuit and a small bias current is very valuable in receiver design. The frequency tuning of a notch filter can be implemented by incorporating varactors into the LC series tank circuit of the notch filter. The capacitance of the tank can then be changed by varying the tuning voltage across the varactor. Unfortunately, it is observed that for a specified choice of tuning voltage, only an optimal current value exists to give the deepest notch response. That means for a different tuning voltage to attain the deepest notch at a corresponding frequency, different currents are required. The desired notch filter is the one which can achieve a deep notch during a wide frequency band. To solve this problem, a new invention to change the bias current automatically with the tuning voltage is proposed.
In the literature some integrated image rejection filters or notch filters have been implemented for RF applications:    In Chunbing Guo, A. N. L. Chan, and H. C. Luong, “A monolithic 2-V 950-MHz bandpass amplifier with a notch filter for wireless receivers” as referenced above, a monolithic 2 V 950 MHz notch filter has been integrated with a bandpass LNA in a 0.5 μm CMOS process. A Q-enhancement circuit has been adopted to compensate the low Q inductor loss. The notch filter can achieve 50 dB image rejection but consumes a DC current of 25 mA.    An inductorless active notch filter working at a central frequency 1.482 GHz is designed in a 0.5 μm CMOS process in Yuyu Chang, J. Choma, Jr. and J. Wills, “An inductorless active notch filter for RF image rejection”, as referenced above. The notch filter utilizes a two Q-enhancement technique to circumvent the low Q characteristics inherent in the designed feedback circuit, which can provide image signal suppression of 70 dB. However, its power consumption of 35 mW is high.    In H. Samavati, H. R Rategh, and T. H. Lee, “A 5-GHz CMOS wireless LAN receiver front end”, as referenced above, a 5 GHz notch filter integrated with an LNA and used for a wireless LAN receiver has been implemented in a standard 0.24 μm CMOS process. 8.4 mA of current is used for both LNA and notch filter at 2 V Vdd. Only 12 dB image rejection is achieved.    An LC notch filter working at 1.1 GHz is implemented in a 0.35 μm CMOS process in M. H. Koroglu and P. E. Allen, “LC notch filter for image reject applications using on-chip inductors”, as referenced above. Transconductor based Q-enhancement circuits are used and image rejection after Q tuning is 70 dB. The current consumption is over 6 mA.    A 2.5 GHz Monolithic bipolar image rejection filter has been implemented in J. Macedo, M. Copeland, and P. Schvan, “A 2.5 GHz monolithic silicon reject filter”, as referenced above. Using 0.8 μm BiCMOS technology, the filter is integrated with a 1.9 GHz LNA and can achieve better than 50 dB image rejection. The DC current consumption is 3.2 mA at 3 V.    A 5 GHz integrated notch filter has been realized in SiGe process with 50 GHz ƒt in J. W. M. Rogers and C. Plett, “A completely 1.8 Volt 5 GHz tunable image reject notch filter”, as referenced above. It can achieve 70 dB image rejection with a current consumption of 4 mA. The noise figure is 4.2 dB.    In U.S. Pat. No. 6,072,376 (Matsuyoshi et al.), a notch filter is connected to a LNA for eliminating a disturbing signal (e.g. image signal). Both impedance matching and noise figure matching without using an isolator have been achieved and has low-noise characteristics.    In U.S. Pat. No. 6,285,865 (Vorenkamp et al.) and US Patent Application publication 2001/0008430A1 “System And Methods For Providing A Low Power Receiver Design”, an integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. The receiver front end provides a programmable gain low noise amplifier followed by frequency conversion circuits. Frequency conversion circuits use LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation are performed by two on chip phase locked loops (PLL).    In U.S. Pat. No. 6,351,502 (Zargari), a radio-frequency front-end, comprised of a low noise amplifier (LNA), a first mixer, and an I/Q quadrature mixer is described. The LNA amplifies has inductive loads. The first mixer is coupled to the LNA and converts the amplified received signal to an intermediate frequency (IF) signal. The first mixer also has inductive loads. The first frequency is chosen such that an image frequency with the carrier and the frequency of the LO signal is outside the bandwidth of the inductive loads of the LNA. The I/Q quadrature mixer further converts the amplified received signal at the IF to I and Q signals.    In U.S. Pat. No. 6,374,094 (Zappala) [15], a new architecture of a combination of signal circulators and RF bandpass filters is presented, which can selectively notch out sub-bands of the two cellular bands in a cellular radio receiver. Thus the sub-bands can be separately directed to a radio capable of receiving either the A or B-band signals.    In U.S. Pat. No. 6,127,962 (Martinson)[16], a downconversion image rejection mixer is invented. It includes two signal path. The one signal path has a bandpass characteristics centered at the input signal frequency interested, and the other signal path has a bandstop characteristics centered at the same frequency. By choosing one or the other path, useful signal can be downconverted but the image signal will be rejected.    In U.S. Pat. No. 5,625,307 (Scheinberg) [17], a low cost monolithic GaAs upconverter chip for CATV receiver is invented. A novel Gilbert type image-rejecting mixer circuit integrated with two matched inductors is used for image rejection. On chip image rejection filter also have been applied in integrated TV tuner.    U.S. Pat. No. 5,737,035 (Rotzoll) and U.S. Pat. No. 6,177,964 (Birleson et al.) describe circuits similar to U.S. Pat. No. 5,625,307 (Scheinberg) above.